Day 6

Day 6 (15th June 2019)

Today I spent some time understanding the nuances of the Day 4 and Day 5 stuff that I did as I did not get enough time during those days to get a handle of what was happening as I was too involved in getting things to work. Sharing my notes with Dan (@zipcpu) it turns out I accidentally discovered back-to-back bus transactions in WB and was doing that, so my output wasn’t matching the tutorial although it was probably OK.

Played around with the testbench, added a clock divider (works in simulation) to slow things down so that I can try putting this on a FPGA - although I may not have LEDs right now but I’d want to put this on a FPGA and try it out during the next week.

I also added a shim over the module so that I can now put it into an FPGA. I am following the approach outlined here, which I found interesting. There will essentially be three levels here - (i) The WB chaser module itself, (ii) A layer over it covering CLK input, LED output and SW input (this will later contain switch debounce logic as well), and (iii) The top level that will connect the CLK, LED and SW to FPGA pins. I will work on this tomorrow.

That’s all for today. Code can be seen here.