Day 24 (3rd July 2019)
Today I fixed the 6th ZipCPU tutorial so that it now passes formal as well as simulation, one thing that’s missing is to try it out on real hardware. I did some work on getting it to work on hardware today - however the issue is that I don’t have a USB-UART converter handy with me, and I consider it a good thing because it’ll now turn me into the direction of implementing USB-UART on the FPGA directly :) . Turns out there do exist USB-Serial implementations on the TinyFPGA BX board that I am using - see  and .
Implementation  seems to be well documented but it runs off a single clock domain of 48MHz.  has two clock domains, one for the CPU and rest of the logic and the other is the 48MHz domain which runs the USB protocol engine. From a design perspective my feeling is that  is better but  seems to document that it works really well with continuous data flow, and I seem to incline towards  personally. It also seems like a good way to be introduced to clock domain crossing, let’s see where this detour takes me!
Next I have the debounce tutorial by ZipCPU (the 7th one in the series) lined up, and after that I have an idea to combine it with a rotary encoder. This should be fun and interesting to implement, and I think this is enough stuff in the pipeline to cover this week. Let’s see.