Day 27 (6th July 2019)
Today I finally fixed the USB-UART issue and I am able to get messages from the TinyFPGA board to the PC! Turns out I had to introduce some delay into the tx_busy line de-assertion in order to slow down the transmit pipeline. I feel that my hack should suffice for now, however the proper solution will be to bridge the cores through an async FIFO, that I will implement after the 10th tutorial from ZipCPU.
Finally I am ready to move on to the 7th tutorial starting tomorrow.