Day 39 (19th September 2019)
Today marks the 101th day continuously from 9th June 2019, this would have been the day I would announce that I’ve completed the 100 day streak, but the streak of activity was broken, and instead there has been a streak of non-activity as this got deprioritized due to my schedule and commitments during this time.
I realize that anything else I have said to myself and will say here beyond this is only going to sound like excuse and rationalizations for not actively pursuing this. I remember that when I started and posted about #100DayFPGA on reddit, there were people encouraging me and saying “Don’t give up”; yet it’s what happened, based on what you are reading right now. I have to admit that I thought at one point here that “Is 100 days enough for what I have written out in the home page, considering I took so long to get through the first 10 ZipCPU tutorials I had thought I will complete sooner?“. Would it have been better if I just declared it a close right now, and take off the responsibility that came with this challenge?
No, I am keeping this open for now, as I am working on an ECP5 based FPGA board still, that I am not sure I can announce here yet - not working on the Verilog of it right now, but on the RISC-V SoC that’s running on it and I have tried it on Verilator as well. Some time in the future, I want to come back and strike out the last paragraph that I have written in this log.
I know that there will be updates coming on this page. If you read it so far and decide to come back to check in again after a while, thank you for doing that. Until then, this is what it is of #100DayFPGA today. Till the next update.