Day 41 (22nd September 2019)

Spent a few more hours getting familiar with LiteX and the valentyusb core that has been built for the Fomu project. I am yet to load the bitstream into the board still but I made some progress today. The end goal is to get valentyusb’s debug interface into the LiteX SoC, and I estimate it may take me a day more or two. Let’s see.