Day 25 (4th July 2019)

Today I worked on unsuccessfully interfacing the usb_uart module to the working code. Looks like I need an async FIFO to cross clock domains, I tried some logic combinations to not much success, will continue debugging this tomorrow.

Code at - https://github.com/abhishek-kakkar/100DayFPGA/tree/master/day25

Also looks like I completed 25 days - a quarter-way through this sprint. The progress so far has been slower than I expected, there is a lot of ground to cover here. I will carry on.